The present invention relates to electrically erasable and programmable memories, especially EEPROM and FLASH memories (FLASH-EEPROM memories). The present invention relates more particularly to a method for the reading of a binary word in a serial input/output memory.
In the patent EP 712 133, the problem is explained with serial access integrated memories where it is almost impossible to match the speed at which these memories are read with the rates imposed by the synchronous type serial buses. The time Tr given for the reading of the binary word in a serial access memory extends from the time when the last address bit is received by the memory to the time when the first bit of the word designated by this address is sent by the memory. Since the reading of an address bit is generally done in the middle of a clock period and the sending of a data bit is done at the beginning of a clock period, the time Tr is at least equal to half of a clock period. Indeed, the time Tr is about 1.5 clock periods with the Microwire or I2C type bus (a pause of one clock cycle being allowed between the reception of the last address bit and the sending of the first bit word read). This is about 0.5 clock period with an SPI type bus which is the worst case regarding the requirement of speed in the reading of memories.
During the time Tr, the address received has to be applied to the address decoder of the memory. The word designated by the received address has to be read. The word read has to be loaded into an output register with parallel input and serial output, and a shift signal has to be applied to the output register so that the first bit of the word read is sent.
In practice, the above-mentioned problem is due to the clock frequency of the serial bus constantly increasing in recent years with the development of technology. This frequency was generally about 1 MHZ about ten years ago, or the equivalent of a clock period of about one microsecond, giving a read time Tr of about 0.5 microseconds in the worst case (SPI bus). At present, the frequency is often in the range of 20 MHZ, namely the equivalent of a clock period of 50 nanoseconds and a very short reading time Tr of about 25 nanoseconds. A reading time Tr of this kind exceeds the possibilities of many EEPROM or FLASH memories, despite the providing of fast read circuits.
To address this drawback, the patent EP 712 133 describes a read method including the activation of a read operation before all the address bits are received. Since the address bits are received at the rate of the clock signal, the time gain is equal to the period of the clock signal multiplied by the number N of anticipated address bits. Although this method is satisfactory, it calls for the simultaneous reading of M binary words having the same partial address, M being equal to 2N. It is thus necessary, in a read-ahead memory, to provide for a number of read circuits (i.e. sense amplifiers) that is greater than in a conventional memory. For example, it is necessary to provide for sixteen read circuits instead of eight for reading ahead two bytes (N=1, M=2), thirty-two read circuits instead of eight reading ahead four bytes (N=2, M=4), etc.
Read circuits of this kind are complicated and take up a considerable silicon surface area. To be precise, a fast reading circuit takes up a silicon surface area of about a thousand memory cells. Doubling or even quadrupling the number of read circuits has a detrimental effect on the compactness of the memory, and the amount of surface lost amounts to 8,000 to 24,000 memory cells.
The present invention seeks to overcome the drawbacks discussed above. More particularly, it is a goal of the present invention to provide a read-ahead method that can be implemented without increasing the number of read circuits.
Another goal of the present invention is to provide for EEPROM memory architectures and FLASH memory architectures to implement a method of this kind.
To achieve these goals, the present invention provides for a method for the reading of a binary word in a serial input/output memory, comprising reading data in the memory on reception of a partial read address in which there are N least significant bits lacking to form a complete address. The read step comprises: simultaneously reading the P first bits of M words of the memory having the same partial address; when the received address is complete, selecting the P first bits of the word designated by the complete address and delivering these bits at the serial output of the memory; reading P following bits of the word designated by the complete address during the delivery of P previous bits and delivering the P following bits at the serial output of the memory when the P previous bits are delivered.
According to one embodiment, the reading of P following bits is done like the reading of the P first bits, by the simultaneous reading of P following bits of the M words of the memory having the same partial address and by selecting the P following bits of the word designated by the complete address.
According to one embodiment applicable to a memory in which the memory cells are arranged in word lines and bit lines and the bits lines are arranged in columns, the method comprises providing, in the memory, for the following: an address decoder positioned for the simultaneous selection, after application to the decoder of a complete address, of P bit lines of M different columns and an interconnection bus positioned for the connection of each of the selected P bit lines to a read circuit.
According to one embodiment, the read step is performed by the application, to the decoder, of the partial address received and the scanning, on the least significant address inputs of the decoder, of the 2N possible combinations of the N last address bits.
According to one embodiment applicable to a memory comprising cells arranged in word lines and bit lines, with one word line forming a memory page, the method comprises a preliminary step including the recording of M words of a same partial address in M adjacent sub-pages of a memory page, recording each word in P adjacent groups of cells each comprising K/P adjacent sub-groups of cells, K being the number of bits of each word, and recording j and j+1 ranking bits of a word in adjacent groups of cells and j and j+P ranking bits of a word in adjacent sub-groups of cells in such a way that the words are folded in the sub-pages.
According to one embodiment, the read step comprises a pre-selection step including the simultaneous selection, in read mode, in each group of cells of each sub-page of the memory, of all the cells containing the bits of the M words having the same partial address, and a selection step including the connection to a read circuit of the cells containing one of the P targeted bits of each of the M words.
According to one embodiment, the P first bits of each of the words read simultaneously in the memory are most significant bits.
The present invention also relates to an integrated circuit serial input/output memory able to carry out the following operations upon the reception of a partial read address in which there are N least significant bits lacking to form a complete address: simultaneously reading the P first bits of M words of the memory having the same partial address; when the received address is complete, selecting the P first bits of the word designated by the complete address and delivering these bits at the serial output; reading P following bits of the word designated by the complete address during the delivery of P previous bits and delivering these bits at the serial output when the P previous bits are delivered.
According to one embodiment, the memory comprises a selection circuit for the selection of a group of P bits among M groups of P bits read simultaneously, receiving, at a control input, the N least significant bits of the complete address.
According to one embodiment, the memory comprises memory cells arranged in word lines and bit lines, the bit lines being arranged in columns, an address decoder for the selection of the bit lines and an interconnection bus to connect selected bit lines to read circuits, the address decoder is positioned for the simultaneous selection of P bit lines of M different columns of the same partial address and the interconnection bus is positioned for the connection of each of the P bit lines selected to a read circuit.
According to one embodiment, the memory comprises an address scanning circuit positioned for the scanning, during an operation for reading one word, of the 2N possible combinations of the N least significant bits of an address applied to the address decoder.
According to one embodiment, the memory comprises memory cells arranged in word lines and bit lines, a word line forming a memory page, and bit interlacing means positioned in order to: record M words of the same partial address in M adjacent sub-pages of a memory page; record each word in P adjacent groups of cells each comprising K/P adjacent sub-groups of cells, K being the number of bits of each word; and record j and j+1 ranking bits of a word in adjacent groups of cells, and j and j+P ranking bits of a word in adjacent sub-groups of cells in such a way that the words are folded in the sub-pages.
According to one embodiment, the memory comprises an address decoder comprising bit line selection switches, a circuit for the programming of the memory comprising latch circuits (LT) connected at input to a data bus comprising K wires, the programming circuit comprises M times K latches (LT), the bit lines of one and the same sub-group of cells are connected to a common line via selection switches, each common line is connected to the output of a latch, and the latches connected at output to sub-groups of cells of the same rank belonging to different sub-pages are connected to one and the same wire of the data bus.
According to one embodiment, the address decoder comprises an inhibiting circuit for the inhibition, in read mode, of its N least significant address inputs, to simultaneously select all the bit lines corresponding to the bits of all the words of the memory having the same partial address.
According to one embodiment, the common lines of the sub-groups of cells of one and the same group of cells are connected to one and the same read circuit via a multiplexer circuit positioned for the connection to the read circuit of only one common line at a time, designated by a control signal of the multiplexer circuit.
According to one embodiment, the multiplexer circuit is driven by a scanning circuit positioned for the scanning, during an operation of reading a word, of all the multiplexing values of the control signal, in such a way that the common lines of each sub-group of one and the same group of cells are connected to the read circuit one after the other.
According to one embodiment, the memory comprises a memory block, elements peripheral to the memory block and a bit interlacer placed between the serial input and the input of the memory block and positioned so as to present, at the input of the memory block, composite words comprising M groups of P bits of M different binary words.
According to one embodiment, the memory comprises a volatile type buffer memory whose output is connected to the input of the memory block and recorder for the recording, in the buffer memory, of the data elements that have to be recorded in the memory block and then the recording in the memory block of the data elements previously recorded in the buffer memory.
According to one embodiment, the memory comprises a recorder for the recording in the buffer memory of composite words comprising M groups of P bits of M different binary words received in serial form.
According to one embodiment, P is equal to K/M, K being the number of bits included in the words stored in the memory, M being equal to 2N.
According to one embodiment, N is equal to 1 and M is equal to 2.